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MX98726

SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE

Macronix International 

MX98726

32.6 DISMIO

32.7 reserved

Disable MIO decode: Must is reset which enable MIO decode in x 188 and x186 mode.

When MIO decode is enabled, IOB register is defined as IO base address of all on chip

registers are mapped to IO space. When MIO decode is disabled, IOB register is defined

as register's memory base address.

GMAC Configuration B Register: GCB (Reg33h), R/W

Bit

33.1-0

33.3-2

33.5-4

33.7-6

Symbol

TTHD[1:0]

RTHD[1:0]

TBLEN[1:0]

RBLEN[1:0]

Description

Transmit FIFO Threshold : Default is 00

TTHD1

TTHD0

FIFO depth

0

0

1/2

0

1

1/4

1

0

3/4

1

1

reserved

Receive FIFO Threshold : Default is 00

RTHD1 RTHD0

FIFO depth

0

0

1/2

0

1

1/4

1

0

3/4

1

1

reserved

Transmit FIFO burst length : Default is 00

TBLEN1 TBLEN0

Burst Length

0

0

4

0

1

8

1

0

12

1

1

16

Receive FIFO burst length : Default is 00

RBLEN1 RBLEN0

Burst Length

0

0

4

0

1

8

1

0

12

1

1

16

Reserved (Reg34h/35h/36h/37h), R/W

aggressiveness

medium

least

most

reserved

aggressiveness

medium

most

least

reserved

Bit

34.7-0

35,7-0

36.7-0

38.8-0

34.7-0

35,7-0

36.7-0

37.7-0

P/N:PM0555

Symbol

Reserved

Description

Reserved

MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.

19

REV. 0.9.8, FEB. 14, 2000

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