MX98726 Ver la hoja de datos (PDF) - Macronix International
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MX98726 Datasheet PDF : 55 Pages
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MX98726
MISC Control Register : MISC1, Reg3Dh, R/W, default=3Ch
Bit
Symbol
3D.0 reserved
3D.1 DISLDMA*
3D.2 TPF
3D.3 TPH
3D.4 TXF
3D.5 TXH
3D.6 TXFIFORST
3D.7 RXFIFORST
Description
reserved
Disable Local DMA arbitration : Default is 0 after reset, meaning local DMAs are
enabled in the SRAM bus arbitration. Set to disable the local DMA arbitration only
when the Reg02h.0 TEST bit is also set. It is used to force the overrun or the
underrun error for the test purpose.
10 Base-T Port Full Duplex capability bit in the linkcode word : Default is set to
enable advertising the 10 Base-T Full duplex capability. Reset to disable advertis-
ing this capability in the outgoing NWAY's linkcode word.
10 Base-T Port Half Duplex capability bit in the linkcode word : Default is set to
enable advertising the 10 Base-T Half duplex capability. Reset to disable advertis-
ing this capability in the outgoing NWAY's linkcode word.
100 Base-TX Full Duplex capability bit in the linkcode word : Default is set to enable
advertising the 100 Base-TX Full duplex capability. Reset to disable advertising
this capability in the outgoing NWAY's linkcode word.
100 Base-TX Half Duplex capability bit in the linkcode word ; Default is set to
enable advertising the 100 Base-TX Half duplex capability. Reset to disable adver-
tising this capability in the outgoing NWAY's linkcode word.
TX FIFO Reset control : Writing a 1 to this bit will clear the TX FIFO, reset all the
current TX FIFO's internal pointers and related byte counters and bring the TX DMA
back to the idle state.
RX FIFO Reset control : Writing a 1 to this bit will clear the RX FIFO, reset all the
current RX FIFO's internal pointers and related byte counters and bring the RX
DMA back to the idle state.
TX FIFO Byte Counter (Direct FIFO Mode) : TXFIFOCNT, Reg3F/3Eh, R/W
Bit
3E.7-0
3F.3-0
Symbol
Description
TXFIFOCNT[7:0] TX FIFO Send Byte Count bit [7:0]: Together with TXFIFOCNT[11:8] forms a 12
bits TX FIFO byte count for direct FIFO mode.
TXFIFOCNT[11:8] TX FIFO Send Byte Count bit [11:8]: Together with TXFIFOCNT[7:0] forms a 12
bits TX FIFO byte count for direct FIFO mode.
Reser ved ( Reg 40h-43h ), RO
Bit
Reserved
Symbol
Description
Register 40h[7:0] to register43h[7:0] are all reserved.
ID1 (Reg45h/44h), RO, default="MX"
Bit
44.7-0,
45.7-0
P/N:PM0555
Symbol
Description
ID1[15:0]
ID1 16 bit code : Reg45h is MSB byte is set to "M", Reg44h is LSB byte is
set to "X".
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
21
REV. 0.9.8, FEB. 14, 2000
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