MX98741 Ver la hoja de datos (PDF) - Macronix International
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MX98741 Datasheet PDF : 34 Pages
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MX98741
A. Command Register (register #0) (R/W)
Table 5-1 Control Register Bit Definition
Bit(s) Name
Description
R/W
0.15 Reset
1 : PHY reset. A 240ns reset pulse will be generated to
reset XRC internal logic.
R/W
0 : normal operation
SC
0.14 Loop Back
1 : enable loopback mode.
0 : disable loopback mode.
The default setting is 0.
R/W
0.13 Speed Selection
Forced to 1 and indicate 100 Mb/s.
Write 0 to this bit has no effect.
R
0.12 Auto-Negotiation Enable Forced to 0 and indicate that Auto-Negotiation process
is disabled.
Write 1 to this bit has no effect.
R
0.11 Power-Down
1 : power-down. COCLK and TXCLK for each port will be
disabled. Clock for Management Block will keep running.
During power-down, all state machines will be reset to its
default state.
0 : normal operation.
R/W
0.10 Isolate
1 : electrically Isolate PHY from MII
0 : normal operation
R/W
0.9
Restart
Forced to 0 and indicate that Auto-Negotiation process
Auto-Negotiation
is disable.
Write 1 to this bit has no effect.
R
0.8
Duplex Mode
Forced to 0 and indicate that only Half Duplex is available.
Write 1 to this bit has no effect.
R
0.7
Collision Test
1 : enable COL signal test. The PHY will assert the
COL signal within 5120 ns in response to the assertion of
TXEN. While this bit is set to one, the PHY will deassert
the COL signal within 40 ns in response to the deassertion
of TXEN.
0 : normal operation.
Set to 0 after power on reset.
R/W
0.6:0 Reserved
Value 0 will be read when one tries to read these bits.
R
P/N:PM0342
REV. 1.4, NOV. 07, 1996
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