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74F299

8-bit universal shift/storage register (3-State)

Philips Electronics 

Philips Semiconductors

8-bit universal shift/storage register (3-State)

Product specification

74F299

FEATURES

• Common parallel I/O for reduced pin count

• Additional serial inputs and outputs for expansion

• Four operating modes: Shift left, shift right, load and store

• 3-State outputs for bus-oriented applications

DESCRIPTION

The 74F299 is an 8-bit universal shift/storage register with 3-State

outputs. Four modes of operation are possible: Hold (store), shift

left, shift right and parallel load. The parallel load inputs and flip-flop

outputs are multiplexed to reduce the total number of package pins.

Additional outputs are provided for flip-flops Q0 and Q7 to allow

easy serial cascading. A separate active-Low Master Reset is used

to reset the register.

The 74F299 contains eight edge-triggered D-type flip-flops and the

interstage logic necessary to perform synchronous shift left, shift

right, parallel load and hold operations. The type of operation is

determined by S0 and S1, as shown in the Function Table. All

flip-flop outputs are brought out through 3-State buffers to separate

I/O pins that also serve as data inputs in the parallel load mode.

Q0 and Q7 are also brought out on other pins for expansion in serial

shifting of longer words.

A Low signal on MR overrides the Select and CP inputs and resets

the flip-flops. All other state changes are initiated by the rising edge

of the clock. Inputs can change when the clock is in either state

provided only that the recommended setup and hold times, relative

to the rising edge of clock are observed.

A High signal on either OE0 or OE1 disables the 3-State buffers and

puts the I/O pins in the high impedance state. In this condition the

shift, hold, load and reset operations can still occur. The 3-State

buffers are also disabled by High signals on both S0 and S1 in

preparation for a parallel load operation.

PIN CONFIGURATION

S0 1

OE0 2

OE1 3

I/O6 4

I/O4 5

I/O2 6

I/O0 7

Q0 8

MR 9

GND 10

20 VCC

19 S1

18 DS7

17 Q7

16 I/O7

15 I/O5

14 I/O3

13 I/O1

12 CP

11 DS0

SF00865

TYPE

74F299

TYPICAL fMAX

115MHz

TYPICAL

SUPPLY CURRENT

(TOTAL)

58mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

20-pin plastic DIP

COMMERCIAL

RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

N74F299N

20-pin plastic SOL

N74F299D

20-pin plastic SSOP II

N74F299DB

PKG DWG #

SOT146-1

SOT163-1

SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

DS0

Serial data input for right shift

1.0/1.0

DS7

Serial data input for left shift

1.0/1.0

S0, S1

Mode select inputs

1.0/2.0

CP

Clock pulse input (Active rising edge)

1.0/1.0

MR

Asynchronous Master Reset input (Active Low)

1.0/1.0

OE0, OE1 Output Enable input (Active Low)

1.0/1.0

Q0, Q7

Serial outputs

50/33

Multiplexed parallel data inputs or

I/On

3-State parallel outputs

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state.

3.5/1.0

150/40

LOAD VALUE

HIGH/LOW

20µA/0.6mA

20µA/0.6mA

20µA/1.2mA

20µA/0.6mA

20µA/0.6mA

20µA/0.6mA

1.0mA/20mA

70µA/0.6mA

3.0mA/24mA

1990 Mar 01

2

853-0365 98989

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