HI5721-EVS(1999) Ver la hoja de datos (PDF) - Intersil

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HI5721-EVS
(Rev.:1999)

10-Bit, 125 MSPS, High Speed D/A Converter

Intersil 

Timing Diagrams

HI5721

CLK

D9-D0

IOUT

50%

1/2 LSB ERROR BAND

V

GLITCH AREA = 1/2 (H x W)

HEIGHT (H)

WIDTH (W)

t (ps)

tPD

tSETT

FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM

CLK

D9-D0

IOUT

tPW1

tPW2

tSU

tSU

tHLD

tPD

FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT

METHOD

tSU

tHLD

tHLD

tSETT

50%

tSETT

tPD

tPD

tSETT

FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

3-39

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