NCP5050(2007) Ver la hoja de datos (PDF) - ON Semiconductor
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NCP5050 Datasheet PDF : 14 Pages
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NCP5050
DETAIL OPERATING DESCRIPTION
4.7uF X5R 6.3V
C1
2.7 to 5.5 V
PVIN
1
L1
2.7 mH
SW
10
UVLO
OVP
-
COMP
UVLO
OVP COMP+
UVLO REF +
MAX DUTY
- OVP REF
CYCLE COMP
THERMAL
FB
M DUTY REF - MAX D
PROTECTION
+
FB
-
FB REF
+
PWM
- COMP
RST
+
Driver
RAMP
COMP
ONE
SHOT
OSC
1.7 MHz
TIME
OUT
SET
IPEAK MAX
250k
IPEAK
COMP
SENSE
CURRENT
REF
MBR130LSF
1uF X5R 0805 25V
D1
C2
Cout
2
VS
D2
750mW
FB
D5
7
250mW
CM
4
FLASH/TORCH
ENABLE
3
CTRL
5
PCA
2.8k
RPCA
1
6
PGND
2.0
RHCS
8
10.0
RLCS
Figure 18. Functional Block Diagram
Operation
The NCP5050 DC-DC converter is based on a Current
Mode PWM architecture which regulates the feedback
voltage at 250 mV under normal operating conditions. The
boost converter operates in two separate phases (See
Figure 19). The first one is TON when the inductor is charged
by current from the battery to store up energy, followed by
TOFF step where the power is transmitted through the
external rectifier to the load. The capacitor COUT is used to
store energy during the TOFF time and to supply current to
the load during the TON stage thus constantly powering the load.
Start
Cycle
SW
588 ns
IL
Ton
Toff
Ipeak
Ivalley
Iout
The internal oscillator provides a 1.7 MHz clock signal to
trigger the PWM controller on each rising edge (SET signal)
which starts a cycle. During this phase the low side NMOS
switch is turned on thus increasing the current through the
inductor. The switch current is measured by the SENSE
CURRENT and added to the RAMP COMP signal. Then
PWM COMP compares the output of the adder and the
signal from ERROR AMP. When the comparator threshold
is exceeded, the NMOS switch is turned off until the rising
edge of the next clock cycle. In addition there are five
functions which can reset the flip-flop logic to switch off the
NMOS. The MAX DUTY CYCLE COMP monitors the
pulse width and if it exceeds 94% (nom) of the cycle time the
switch will be turned off. This limits the switch from being
on for more than one cycle. Thank to IPEAK COMP, the
current through the inductor is monitored and compared
with the IPEAK_MAX threshold setup by RPCA (See Inductor
Selection). If the current exceeds this threshold the
controller is will turn off the NMOS switch for the remainder
of the cycle. This is a safety function to prevent any
excessive current that could overload the inductor and the
power stage. The three other safety circuits are, OVP,
UVLO, and THERMAL PROTECTION. Please refer to the
details in following sections.
The loop stability is compensated by the ERROR AMP
built in integrator. The gain and the loop bandwidth are fixed
Figure 19. Basic DC-DC Operation
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