NCV8668 Ver la hoja de datos (PDF) - ON Semiconductor

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NCV8668

LDO Regulator - Very Low Iq, Window Watchdog, Enable and Reset 150 mA

ON Semiconductor 

NCV8668

a pull−up resistor (30 kW) internally connected to the output

(VOUT). No external pull−up is necessary.

For voltage option 3.3 V RO is open drain output and

external pull−up resistor is required.

Reset signal is also generated in case when input voltage

decreases below its minimum operating limit (4.5 V). The

Input Voltage Reset Threshold is typically 3.8 V. This

applies only to voltage options with nominal value below

minimum operating input voltage (3.3 V).

Window Watchdog Operation

The watchdog slow, fast or off state is set by pins WM1

and WM2 (see table in Figure 25). The timing values used

in this description refer to typ. Values when WM1 and WM2

are connected to GND (fast watchdog and reset timing). The

state diagram of the window watchdog (WWD) and the

watchdog and reset mode selection table is shown in

Figure 25. The WWD timing is shown in Figure 26. After

power−on, the reset output signal at the RO pin

(microprocessor reset) is kept LOW for the reset delay time

tRD (16 ms). RO signal transition from LOW to HIGH

triggers the ignore window (IW) with duration of tIW

(32 ms). During this window the signal at the WDI pin is

ignored. When IW ends a long open window with maximum

duration of (128 ms, tmax = 4xtOW) is started. When a valid

trigger signal is detected during long open window, a closed

window (CW) with duration of tCW (32 ms) is initialized

immediately. WDI signal transition from HIGH to LOW is

taken as a trigger. As valid trigger two HIGH samples

followed by two LOW samples (with sampling time tsam =

0.5 ms) have to be present before end of the long window.

Valid WDI trigger signal is shown in Figure 27. When CW

ends a standard open window (OW) with maximum duration

of tOW (32 ms) is initiated immediately. The OW ends

immediately when valid trigger appears at WDI input. For

normal operation the microprocessor timing of WDI pulses

must be stable and correspond to tWD. A reset signal is

generated (RO goes LOW) if there is no valid trigger

(missing pulse at WDI pin) during OW or if a pre−trigger

occurs during the CW (unexpected pulse at WDI pin).

Thermal Considerations

As power in the NCV8668 increases, it might become

necessary to provide some thermal relief. The maximum

power dissipation supported by the device is dependent

upon board design and layout. Mounting pad configuration

on the PCB, the board material, and the ambient temperature

affect the rate of junction temperature rise for the part. When

the NCV8668 has good thermal conductivity through the

PCB, the junction temperature will be relatively low with

high power applications. The maximum dissipation the

NCV8668 can handle is given by:

ƪ ƫ TJ(MAX) * TA

PD(MAX) +

RqJA

(eq. 1)

Since TJ is not recommended to exceed 150°C, then the

NCV8668 soldered on 645 mm2, 1 oz copper area, FR4 can

dissipate up to 1.3 W for SOIC−14 package when the

ambient temperature (TA) is 25°C. See Figure 28 for RqJA

versus PCB area. The power dissipated by the NCV8668 can

be calculated from the following equations:

PD + VinǒIq@IoutǓ ) IoutǒVin * VoutǓ

(eq. 2)

or

PD(MAX) ) ǒVout

Vin(MAX) +

Iout ) Iq

IoutǓ

(eq. 3)

140

SOIC−14

130

120

110

100

PCB 1 oz Cu

90

PCB 2 oz Cu

80

0 100 200 300 400 500 600 700

COPPER HEAT SPREADER AREA (mm2)

Figure 28. Thermal Resistance vs PCB Copper Area

Hints

Vin and GND printed circuit board traces should be as

wide as possible. When the impedance of these traces is

high, there is a chance to pick up noise or cause the regulator

to malfunction. Place external components, especially the

output capacitor, as close as possible to the NCV8668, and

make traces as short as possible.

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