NM95MS18 Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Lista de partido
NM95MS18
Fairchild Semiconductor
NM95MS18 Datasheet PDF : 12 Pages
| |||
Internal EEPROM Memory of
NM95MS18 (Continued)
resource allocation probabilities and also allows presence of
multiple cards of the same type. Each IRQOUTx signal can be
individually set for either Interrupt type and this is done by setting
Details of timing information for Microwire protocol can be ob-
tained from Fairchild’s Microwire EEPROM Datasheets. Please
appropriate bits in EEPROM register. Refer the USER’S GUIDE
for more detail.
refer NM93C66 datasheet. This datasheet can be downloaded
from Fairchild’s home page on World-Wide-Web. (http://
Wire-ANDing of I/O Chipselects
www.fairchildsemi.com)
The IOCS1* and IOCS2* signals can be internally Wire-ANDed
with IOCS0* signal on NM95MS18. When this feature is enabled,
SHARING OF INTERRUPTS
IOCS0* signal can also act as “Output Enable” signal for ISA bus
Interrupt output (IRQOUTx) signals from NM95MS18 can be
configured as either standard TTL type or Open-Drain type.
Interrupt outputs configured as Open-Drain type can share an
interrupt on the ISA bus. Sharing of interrupt increases ISA bus
data buffers eliminating extra glue logic on the board. Setting
appropriate bits in EEPROM register enables this feature. Refer
the USER’S GUIDE for more detail. Following diagram illustrates
this feature.
WIRE-ANDing of I/O Chipselects
,,, SA[0:15]
IORD*/IOWR
Base Address
for IOCS0
Base Address
for IOCS1
Base Address
for IOCS2
IOCS0*
IOCS1*
IOCS2*
IOCS1* Wire-ANDed
with IOCS0*
IOCS2* Wire-ANDed
with IOCS0*
Note 1: This illustratory waveform assumes that both IOCS1* and IOCS2* are set to be Wire-ANDed with IOCS0*. They can also be set individually.
Note 2: In this waveform, IOCSx* are set to be decoded off of address and IORD*/IOWR.
Note 3: Refer “I/O DECODE QUALIFICATION REGISTER” description for more information.
DS500033-11
11
www.fairchildsemi.com
Share Link: