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PCD4440T

Analog voice scrambler/descrambler

Philips Electronics 

Philips Semiconductors

Analog voice scrambler/descrambler

Product specification

PCD4440T

Table 2 Explanation of time symbols used in Fig.10

SYMBOL

PARAMETER

fSCL

SCL clock frequency

tSW

tolerable pulse spike width

tBUF

bus free time

tSU;STA

tHD;STA

tLOW

tHIGH

tr

tf

tSU;DAT

tHD;DAT

tSU;STO

set-up time repeated START

hold time START condition

SCL LOW time

SCL HIGH time

rise time SDA and SCL

fall time SDA and SCL

data set-up time

data hold time

set-up time STOP condition

DESCRIPTION

The time that the bus is free (SDA is HIGH)

before a new transmission is initiated by

SDA going LOW.

Only valid for repeated start code.

The time between SDA going LOW and the

first valid negative-going transition of SCL.

The LOW period of the SCL clock.

The HIGH period of the SCL clock.

MIN.

0

−

4.7

4.7

4.0

4.7

4.0

−

−

250

0

4.0

MAX.

100

100

−

−

−

−

−

1.0

0.3

−

−

−

UNITS

kHz

ns

µs

µs

µs

µs

µs

µs

µs

ns

ns

µs

1996 Dec 20

12

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