LP62S1024B-I Ver la hoja de datos (PDF) - AMIC Technology
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LP62S1024B-I Datasheet PDF : 17 Pages
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LP62S1024B-I Series
128K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
Power supply range: 2.7V to 3.6V
Access times: 45/55/70 ns (max.)
Current:
Very low power version: Operating: 30mA(max.)
Standby: 5uA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention voltage: 1.5V (min.)
Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)
forward type and 36-pin CSP packages
All Pb-free (Lead-free) products are RoHS compliant
General Description
The LP62S1024B-I is a low operating current 1,048,576-bit
static random access memory organized as 131,072 words
by 8 bits and operates on a low power voltage: 2.7V to 3.6V.
It is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included for
easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 1.5V.
Product Family
Product Family Operating
Temperature
VCC
Range
Speed
Power Dissipation
Data Retention Standby Operating
(ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.)
LP62S1024B -40°C ~ +85°C 2.7V~3.6V 45ns/55ns/70ns
0.05μA
0.08μA
1.5mA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 1.5V.
Package
Type
32L SOP
32L TSOP
32L TSSOP
36B μBGA
(December, 2008, Version 1.4)
1
AMIC Technology, Corp.
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