P4C1023-70CWC Ver la hoja de datos (PDF) - Semiconductor Corporation
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P4C1023-70CWC Datasheet PDF : 11 Pages
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P4C1023/P4C1023L
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
Output Timing Reference Level
1.5V
1.5V
Output Load
See Figures 1 and 2
TRUTH TABLE
Mode
CE OE WE
Standby H X X
DOUT Disabled L H H
Read
LLH
Write
LXL
I/O
High Z
High Z
DOUT
DIN
Power
Standby
Active
Active
Active
* including scope and test fixture.
Note:
Because of the high speed of the P4C1023L, care must be taken when
testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with DOUT to match 639Ω
(Thevenin Resistance).
Document # SRAM126 REV OR
Page 6 of 11
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