P4C1024-17J3I Ver la hoja de datos (PDF) - Semiconductor Corporation
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P4C1024-17J3I Datasheet PDF : 14 Pages
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P4C1024
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-15
-20
-25
-35
-45
-55
-70
-85
-100
-120
Symbol Parameter Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
tRC
Read Cycle
Time
15
20
25
35
45
55
70
85
100
120
ns
tAA
Address
Access Time
15
20
25
35
45
55
70
85
100
120 ns
tAC
Chip Enable
Access Time
15
20
25
35
45
55
70
85
100
120 ns
Output Hold
tOH from Address 3
3
3
3
3
3
3
3
3
3
ns
Change
tLZ
Chip Enable to
Output in Low Z
3
3
3
3
3
3
3
3
3
3
ns
Chip Disable
tHZ to Output in
High Z
8
9
11
15
20
25
30
35
40
50 ns
Output Enable
tOE Low to Data
Valid
7
9
11
15
20
25
30
35
40
50 ns
tOLZ
Output Enable
Low to Low Z
0
0
0
0
0
0
0
0
0
0
ns
tOHZ
Output Enable
High to High Z
7
9
11
15
20
25
30
35
40
50 ns
Chip Enable to
tPU Power Up
0
0
0
0
0
0
0
0
0
0
ns
Time
Chip Disable
tPD to Power Down
12
20
20
20
25
30
35
40
45
50 ns
Time
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
Notes:
5. WE is HIGH for READ cycle.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1 transition
LOW and CE2 transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
Document # SRAM124 REV A
Page 4 of 14
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