P4C1024L-55TC Ver la hoja de datos (PDF) - Semiconductor Corporation
Número de pieza
componentes Descripción
Lista de partido
P4C1024L-55TC Datasheet PDF : 11 Pages
| |||
P4C1024L
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Fig. 1 and 2
TRUTH TABLE
Mode
Standby
Standby
CE1 CE2 OE WE
H XXX
X LXX
DOUT Disabled L H H H
Read
LHLH
Write
L HX L
I/O
High Z
High Z
High Z
DOUT
DIN
Power
Standby
Standby
Active
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the high speed of the P4C1024L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the VCC
and ground planes directly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required between VCC and ground.
Figure 2. Thevenin Equivalent
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with DOUT to match 639Ω
(Thevenin Resistance).
Document # SRAM125 REV C
Page 6 of 10
Share Link: 