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Semiconductor
TIMING DIAGRAM
Write Cycle Timing (Write Reset)
tWSWH
tSWC
SWCK
tRSTWS
tWSWL
tRSTWH
RSTW
tDS
tDH
DI 0-15
Dn-1 Dn
tFWD
WE
tLWE
MS81V06160
0 cycle
tWL
D0
D1
IE
*After write reset, WE should be remained high for 2 cycles after driving WE high first.
Write Cycle Timing (Write Enable)
1 cycle 2 cycle 3cycle
4 cycle 5 cycle 6 cycle
SWCK
tWWEL
tWWEH
WE
DI 0-15
tWENH
D0
D1
tWDSH
D2
D3
tWDSS
tWEL
RSTW L
IE
H
tWENS
D4
D5
D6
D7
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