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IA8044

SDLC Communications Controller

InnovASIC, Inc 

IA8044/IA8344

SDLC Communications Controller

Data Sheet

March 30, 2010

4.3 Memory Organization

4.3.1 Program Memory

Program Memory includes interrupt and Reset vectors. The interrupt vectors are spaced at 8-byte

intervals, starting from 0003H for External Interrupt 0.

Table 6. Reset Vectors

Location

0003H

000BH

0013H

001BH

0023H

Service

External Interrupt 0

Timer 0 overflow

External Interrupt 1

Timer 1 overflow

SIU Interrupt

These locations may be used for program code, if the corresponding interrupts are not used

(disabled). The program memory space is 64K, from 0000H to FFFFH. The lowest 4K of

program code (0000H to 0FFFH) can be fetched from external or internal program memory. This

selection is made by strapping pin ―EA‖ (External Address) to GND or VCC. If during reset

―EA‖ is held low, all the program code is fetched from external memory. If during reset ―EA‖ is

held high, the lowest 4K of program code (0000H to 0FFFH) is fetched from internal memory

(ROM). Program memory addresses above 4K (0FFFH) will cause the program code to be

fetched from external memory regardless of the setting of ―EA.‖

4.3.2 External Data Memory

The IA8044/IA8344 Microcontroller core incorporates the Harvard architecture, with separate

code and data spaces. The code from external memory is fetched by ―psen‖ strobe, while data

is read from RAM by Bit [7] of P3 (read strobe) and written to RAM by Bit [6] of P3 (write

strobe). The External Data Memory space is active only by addressing through use of the MOVX

instruction and the 16-bit Data Pointer Register (DPTR). A smaller subset of external data

memory (8-bit addressing) may be accessed by using the MOVX instruction with register indexed

addressing.

4.3.3 Internal Data Memory

As presented in Figure 6, the Internal Data Memory address is always one byte wide. The

memory space is 192 bytes large (00H to BFH), and can be accessed by either direct or indirect

addressing. The special function registers (SFRs) occupy the upper 128 bytes. This SFR area is

available only by direct addressing. Internal memory that overlaps the SFR address space is only

accessible by indirect addressing.

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