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PA7536

PEEL Array™ Programmable Electrically Erasable Logic Array

Anachip Corporation 

PEEL™ Array Development Support

Development support for PEEL™ Arrays is provided by

Anachip and manufacturers of popular development tools.

Anachip offers the powerful PLACE Development Software

(free to qualified PLD designers). The PLACE software

includes an architectural editor, logic compiler, waveform

simulator, documentation utility and a programmer

interface. The PLACE editor graphically illustrates and

controls the PEEL™ Array’s architecture, making the

overall design easy to understand, while allowing the

effectiveness of boolean logic equations, state machine

design and truth table entry. The PLACE compiler performs

logic transformation and reduction, making it possible to

specify equations in almost any fashion and fit the most

logic possible in every design. PLACE also provides a

multi-level logic simulator allowing external and internal

signals to be simulated and analyzed via a waveform

display.(See Figure 12, Figure 13 and Figure 14)

waste. Programming of PEEL™ Arrays is supported by

popular third party programmers.

Design Security and Signature Word

The PEEL™ Arrays provide a special EEPROM security bit

that prevents unauthorized reading or copying of designs.

Once set, the programmed bits of the PEEL™ Arrays

cannot be accessed until the entire chip has been

electrically erased. Another programming feature,

signature word, allows a user-definable code to be

programmed into the PEEL™ Array. The code can be read

back even after the security bit has been set. The signature

word can be used to identify the pattern programmed in the

device or to record the design revision.

Figure 13 - PLACE LCC and IOC screen

Figure 12 - PLACE Architectural Editor for

PA7536

PEEL™ Array development is also supported by popular

development tools, such as ABEL and CUPL, via ICT’s

PEEL™ Array fitters. A special smart translator utility adds

the capability to directly convert JEDEC files for other

devices into equivalent JEDEC files for pin-compatible

PEEL™ Arrays.

Programming

PEEL™ Arrays are EE-reprogrammable in all package

types, plastic-DIP, PLCC and SOIC. This makes them an

ideal development vehicle for the lab. EE-

reprogrammability is also useful for production, allowing

unexpected changes to be made quickly and without

5

Figure 14 - PLACE simulator screen

04-02-052A

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