RESET 2
DATA 3
VDD
MC14599B
FUNCTION DIAGRAM
11 Q0
VSS
CHIP
ENABLE
8
WRITE/READ 10
WRITE
DISABLE
4
A0 5
A1 6
A2 7
(M.S.B.)
TO
OTHER
LATCHES
ZERO
SELECT
EACH LATCH
ADDRESS
DECODER
OTHER LATCHES
12 Q1
13 Q2
14 Q3
15 Q4
16 Q5
17 Q6
1 Q7
TRUTH TABLE
Chip
Enable
Write/Read
Write
Disable
Reset
Addressed
Latch
0
X
X
0
*
1
1
0
0
Data
1
1
1
0
*
1
0
X
0
*
X
X
X
1
0
X = Don’t care.
* = No change in state of latch.
Z = High impedance.
Qn = State of addressed latch.
Other
Latches
*
*
*
*
0
Data
Pin
Z
Input
Z
Qn
Z/0
CAUTION: To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on
the address inputs A0, A1, and A2.
MC14099B MC14599B
250
MOTOROLA CMOS LOGIC DATA