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SL74HC323

8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS

System Logic Semiconductor 

SL74HC323

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

Symbol

Parameter

Test Conditions

VIH

Minimum High-Level VOUT=0.1 V or VCC-0.1 V

Input Voltage

IOUT≤ 20 µA

VIL

Maximum Low -Level VOUT=0.1 V or VCC-0.1 V

Input Voltage

IOUT ≤ 20 µA

VOH

Minimum High-Level VIN=VIH or VIL

Output Voltage

IOUT ≤ 20 µA

VIN=VIH or VIL

IOUT ≤ 6.0 mA (P/Q)

IOUT ≤ 7.8 mA (P/Q)

VIN=VIH or VIL

IOUT ≤ 4.0 mA (Q’)

IOUT ≤ 5.2 mA (Q’)

VOL

Maximum Low-Level VIN= VIL or VIH

Output Voltage

IOUT ≤ 20 µA

VIN=VIH or VIL

IOUT ≤ 6.0 mA (P/Q)

IOUT ≤ 7.8 mA (P/Q)

VIN=VIH or VIL

IOUT ≤ 4.0 mA (Q’)

IOUT ≤ 5.2 mA (Q’)

IIN

Maximum Input

Leakage Current

VIN=VCC or GND

IOZ

Maximum Three-State Output in High-Impedance

Leakage Current

State

(QA thru QH)

VIN= VIL or VIH

VOUT=VCC or GND

ICC

Maximum Quiescent VIN=VCC or GND

Supply Current

IOUT=0µA

(per Package)

VCC

Guaranteed Limit

V 25 °C ≤85 ≤125 Unit

to

°C °C

-55°C

2.0 1.5 1.5 1.5

V

4.5 3.15 3.15 3.15

6.0 4.2 4.2 4.2

2.0 0.3 0.3 0.3

V

4.5 0.9 0.9 0.9

6.0 1.2 1.2 1.2

2.0 1.9 1.9 1.9

V

4.5 4.4 4.4 4.4

6.0 5.9 5.9 5.9

4.5 3.98 3.84 3.7

6.0 5.48 5.34 5.2

4.5 3.98 3.84 3.7

6.0 5.48 5.34 5.2

2.0 0.1 0.1 0.1

V

4.5 0.1 0.1 0.1

6.0 0.1 0.1 0.1

4.5 0.26 0.33 0.4

6.0 0.26 0.33 0.4

4.5 0.26 0.33 0.4

6.0 0.26 0.33 0.4

6.0 ±0.1 ±1.0 ±1.0 µA

6.0 ±0.5 ±5.0 ±10 µA

6.0 8.0

80 160 µA

SLS

System Logic

Semiconductor

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