¡ Semiconductor
MSM80C88A-10RS/GS/JS
Asynchronous Signal Recognition
CLK
NMI
INTR Signal
TEST
tINVCH (See NOTE 1)
NOTE: 1 Setup requirements for asynchronous
signals only to guarantee recognition
at next CLK
Bus Lock Signal Timing (Maximum Mode Only)
CLK
LOCK
Any CLK Cycle
Any CLK Cycle
tCLAV
tCLAV
Reset Timing
VCC
CLK
Reset
≥ 50msec
tDVCLtCLDX
≥ 4 CLK Cycles
Request/Grant Sequence Timing (Maximum Mode Only)
Any CLK Cycle
> 0 CLK Cycle
CLK
tCLGH
RQ/GT
≥ tCLCL
tGVCH
tCHGX
Pulse 1
Coprocessor
RQ
AD7 - AD0, A15 - A8
A19/S6 - A16/S3
S2, S1, S0,
RD, COCK
Previous Grant
MSM80C88A-10
tCLGL
Pulse 2
MSM80C88
GT
tCLG≥HtCLCL
Pulse 3
Coprocessor
Release
tCLAZ
Coprocessor
(See NOTE 1)
NOTE: 1 The coprocessor may not drive the busses outside
the region shown without risking contention
MSM80C88A-10
Hold/Hold Acknowledge Timing (Minimum Mode Only)
CLK
HOLD
HLDA
AD7 - AD0, A15 - A8
A19/S6 - A16/S3
RD
IO/M
DT/R, WR, DEN
£ 1 CLK Cycle
1 or 2 Cycles
tHVCH
MSM80C88A-10
tHVCH
tCLHAV
tCLAZ
Coprocessor
tCLHAV
MSM80C88A-10
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