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PCA9515D Datasheet PDF : 16 Pages
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NXP Semiconductors
PCA9515
I2C-bus repeater
7. Application design-in information
A typical application is shown in Figure 4. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz
unless the slave bus is isolated and then the master bus can run at 400 kHz. Master
devices can be placed on either bus.
3.3 V
5V
SDA
SCL
BUS
MASTER
400 kHz
VCC
SDA0
SCL0
SDA1
SCL1
PCA9515
EN
SDA
SCL
SLAVE
100 kHz
bus 0
Fig 4. Typical application
bus 1
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The PCA9515 is 5 V tolerant so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9515 is pulled LOW by a device on the I2C-bus, a CMOS
hysteresis type input detects the falling edge and causes an internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9515 will typically be at VOL = 0.5 V.
In order to illustrate what would be seen in a typical application, refer to Figure 5 and
Figure 6. If the bus master in Figure 4 were to write to the slave through the PCA9515, we
would see the waveform shown in Figure 5 on Bus 0. This looks like a normal I2C-bus
transmission until the falling edge of the 8th clock pulse. At that point, the master releases
the data line (SDA) while the slave pulls it LOW through the PCA9515. Because the VOL of
the PCA9515 is typically around 0.5 V, a step in the SDA will be seen. After the master
has transmitted the 9th clock pulse, the slave releases the data line.
On the Bus 1 side of the PCA9515, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9515. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events on Bus 1 require that
the VOL of the devices on Bus 1 be 70 mV below the VOL of the PCA9515 (see VOL−VILc in
Section 9 “Static characteristics”) to be recognized by the PCA9515 and then transmitted
to Bus 0.
PCA9515_9
Product data sheet
Rev. 09 — 23 April 2009
© NXP B.V. 2009. All rights reserved.
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