PCA9548A(2009) Ver la hoja de datos (PDF) - NXP Semiconductors.
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PCA9548A Datasheet PDF : 26 Pages
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NXP Semiconductors
PCA9548A
8-channel I2C-bus switch with reset
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
SLAVE
Fig 10. System configuration
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7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
data output
by receiver
SCL from master
1
2
S
START
condition
Fig 11. Acknowledgement on the I2C-bus
not acknowledge
acknowledge
8
9
clock pulse for
acknowledgement
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PCA9548A_3
Product data sheet
Rev. 03 — 7 July 2009
© NXP B.V. 2009. All rights reserved.
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