PCA9561 Ver la hoja de datos (PDF) - Philips Electronics
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PCA9561 Datasheet PDF : 17 Pages
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Philips Semiconductors
Quad 6-bit multiplexed I2C EEPROM DIP switch
Product data sheet
PCA9561
AC CHARACTERISTICS
SYMBOL
PARAMETER
MUX_IN ⇒ MUX_OUT
tPLH
LOW-to-HIGH transition time
tPHL
HIGH-to-LOW transition time
Select ⇒ MUX_OUT
tPLH
LOW-to-HIGH transition time
tPHL
HIGH-to-LOW transition time
tR
Output rise time
tF
Output fall time
CL
Test load capacitance on outputs
MIN.
—
—
—
—
1.0
1.0
—
LIMITS
TYP.
28
8
30
10
—
—
—
MAX.
40
15
43
15
3
3
—
UNIT
ns
ns
ns
ns
ns/V
ns/V
pF
SYMBOL
PARAMETER
STANDARD-MODE
I2C-BUS
MIN
MAX
FAST-MODE I2C-BUS
MIN
MAX
UNIT
fSCL
tBUF
tHD;STA
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
0
100
0
400
kHz
4.7
—
1.3
—
µs
4.0
—
0.6
—
µs
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
tf
tSU;STO
Cb
tSP
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
4.7
—
1.3
—
µs
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
01
3.45
01
0.9
µs
250
—
100
—
ns
—
1000
20 + 0.1Cb2
300
ns
—
300
20 + 0.1Cb2
300
ns
4.0
—
0.6
—
µs
—
400
—
400
pF
—
50
—
50
ns
NOTES:
1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
2. Cb = total capacitance of one bus line in pF.
SDA
tBUF
tLOW
tR
tF
SCL
P
tHD;STA
S
tHD;DAT
tHIGH
tSU;DAT
tHD;STA
tSU;STA
Sr
Figure 10. Definition of timing
tSP
tSU;STO
P
SU00645
2004 May 17
12
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