PCA9564D(2003) Ver la hoja de datos (PDF) - Philips Electronics

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PCA9564D
(Rev.:2003)

Parallel bus to I2C-bus controller

Philips Electronics 

Philips Semiconductors

Parallel bus to I2C-bus controller

Product data

PCA9564

I2C-BUS TIMING DIAGRAMS

The diagrams (Figures 9 to 12) illustrate typical timing diagrams for the PCA9564 in master/slave functions.

SCL

SDA

INT

START

condition

7-bit address

interrupt

R/W = 0

ACK

from slave receiver

Master PCA9564 writes data to slave transmitter.

first-byte

interrupt

ACK

nbyte

ACK

Figure 9. Bus timing diagram; master transmitter mode

interrupt

STOP

condition

su01490

SCL

SDA

INT

START

condition

7-bit address

interrupt

R/W = 1

ACK

from slave

Master PCA9564 reads data from slave transmitter.

first-byte

interrupt

ACK

nbyte

no ACK

from master

receiver

Figure 10. Bus timing diagram; master receiver mode

STOP

condition

su01491

2003 Apr 02

17

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