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PCA9558 Datasheet PDF : 27 Pages
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NXP Semiconductors
PCA9558
8-bit I2C-bus/SMBus I/O port
7.1.3 EEPROM write operation
7.1.3.1 6-bit write operation
A write operation to the 6-bit EEPROM requires that an address byte be written after the
command byte. This address points to the 6-bit address space in the EEPROM array.
Upon receipt of this address, the PCA9558 waits for the next byte that will be written to the
EEPROM. The master then ends the transaction with a STOP condition on the I2C-bus.
See Figure 12.
After the STOP condition, the E/W cycle starts, and the parts will not respond to any
request to access the EEPROM array until the cycle finishes, approximately 4 ms.
slave address
command byte
EEPROM address
S 1 0 0 1 1 1 A0 0 A 0 0 0 0 0 1 0 0 A 1 1 1 1 1 1 1 1 A (cont.)
START condition
R/W acknowledge
from slave
Fig 12. I2C-bus write of 6-bit EEPROM
acknowledge
from slave
acknowledge
from slave
data for 6-bit EEPROM
(cont.)
X
X d5 d4 d3 d2 d1 d0 A
P
programming begins
after STOP
acknowledge STOP
from slave condition
002aad376
7.1.3.2 6-bit read operation
A read operation is initiated in the same manner as a write operation, with the exception
that after the word address has been written a REPEATED START condition is placed on
the I2C-bus and the direction of communication is reversed (see Figure 13).
slave address
command byte
EEPROM address
S 1 0 0 1 1 1 A0 0 A 0 0 0 0 0 1 1 0 A 1 1 1 1 1 1 1 1 A (cont.)
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
slave address
data from 6-bit EEPROM
(cont.) S 1 0 0 1 1 1 A0 1 A 0 0 d5 d4 d3 d2 d1 d0 NA P
(re)START
condition
Fig 13. I2C-bus read of 6-bit EEPROM
R/W acknowledge
from slave
no acknowledge STOP
from master condition
002aad377
PCA9558_4
Product data sheet
Rev. 04 — 14 April 2009
© NXP B.V. 2009. All rights reserved.
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