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PCA9564BS

Parallel bus to I2C-bus controller

NXP Semiconductors. 

Philips Semiconductors

Parallel bus to I2C-bus controller

Product data sheet

PCA9564

Slave Transmitter Mode: In the slave transmitter mode, a number

of data bytes are transmitted to a master receiver (see Figure 5).

Data transfer is initialized as in the slave receiver mode. When

I2CADR and I2CCON have been initialized, SIO waits until it is

addressed by its own slave address followed by the data direction

bit which must be “1” (R) for SIO to operate in the slave transmitter

mode. After its own slave address and the R bit have been received,

the serial interrupt flag (SI) is set and a valid status code can be

read from I2CSTA. This status code is used to vector to an interrupt

service routine, and the appropriate action to be taken for each of

these status codes is detailed in Table 5. The slave transmitter mode

may also be entered if arbitration is lost while SIO is in the master

mode (see state B0H).

If the AA bit is reset during a transfer, SIO will transmit the last byte

of the transfer and enter state C8H. SIO is switched to the not

addressed slave mode and will ignore the master receiver if it

continues the transfer. Thus the master receiver receives all 1s as

serial data. While AA is reset, SIO does not respond to its own slave

address. However, the I2C-bus is still monitored, and address

recognition may be resumed at any time by setting AA. This means

that the AA bit may be used to temporarily isolate SIO from the

I2C-bus.

Miscellaneous States: There are four I2CSTA codes that do not

correspond to a defined SIO hardware state (see Table 6). These

are discussed below.

I2CSTA = F8H:

This status code indicates that no relevant information is available

because the serial interrupt flag, SI, is not yet set. This occurs on a

STOP condition and when SIO is not involved in a serial transfer.

I2CSTA = 00H:

This status code indicates that a bus error has occurred during an

SIO serial transfer. A bus error is caused when a START or STOP

condition occurs at an illegal position in the format frame. Examples

of such illegal positions are during the serial transfer of an address

byte, a data byte, or an acknowledge bit. A bus error may also be

caused when external interference disturbs the internal SIO signals.

When a bus error occurs, SI is set. To recover from a bus error, the

microcontroller must send an external reset signal to reset the SIO.

I2CSTA = 70H:

This status code indicates that the SDA line is stuck LOW when the

SIO, in master mode, is trying to send a START condition.

I2CSTA = 90H:

This status code indicates that the SCL line is stuck LOW.

Some Special Cases: The SIO hardware has facilities to handle the

following special cases that may occur during a serial transfer:

• SIMULTANEOUS REPEATED START CONDITIONS FROM TWO MASTERS

A repeated START condition may be generated in the master

transmitter or master receiver modes. A special case occurs if

another master simultaneously generates a repeated START

condition (see Figure 6). Until this occurs, arbitration is not lost by

either master since they were both transmitting the same data.

If the SIO hardware detects a repeated START condition on the

I2C-bus before generating a repeated START condition itself, it will

use the repeated START as its own and continue with the sending of

the slave address.

• DATA TRANSFER AFTER LOSS OF ARBITRATION

Arbitration may be lost in the master transmitter and master receiver

modes. Loss of arbitration is indicated by the following states in

I2CSTA; 38H, 68H, and B0H (see Figures 2 and 3).

NOTE: In order to exit state 38H, a Timeout, Reset, or external

Stop are required.

If the STA flag in I2CCON is set by the routines which service these

states, then, if the bus is free again, a START condition (state 08H)

is transmitted without intervention by the CPU, and a retry of the

total serial transfer can commence.

• FORCED ACCESS TO THE I2C BUS

In some applications, it may be possible for an uncontrolled source

to cause a bus hang-up. In such situations, the problem may be

caused by interference, temporary interruption of the bus or a

temporary short-circuit between SDA and SCL.

If an uncontrolled source generates a superfluous START or masks

a STOP condition, then the I2C-bus stays busy indefinitely. If the

STA flag is set and bus access is not obtained within a reasonable

amount of time, then a forced access to the I2C-bus is possible. If

the I2C-bus stays idle for a time period equal to the time out period,

then the ’64 concludes that no other master is using the bus and

sends a START condition.

S

SLA

W

A

08H

18H

DATA

A

S

28H

BOTH MASTERS CONTINUE

WITH SLA TRANSMISSION

OTHER MASTER SENDS REPEATED

START CONDITION EARLIER

Figure 6. Simultaneous repeated START conditions from 2 masters

SU00975

2006 Sep 01

15

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