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PCD5041

DECT burst mode controller

Philips Electronics 

Philips Semiconductors

DECT burst mode controller

Objective specification

PCD5041

6.6 Microcontroller Interface

6.6.1 FUNCTION OF THE MICROCONTROLLER INTERFACE

The microcontroller interface will provide the following

services.

• Direct interface to processors which have an

INTEL-8051 compatible interface

• General interface to processors that can handle ‘wait

states’ e.g. 68000-family; in this case glue logic is

required

• Processor clock signal of which the frequency is

programmable in order to adjust instantaneously

processor performance to processor work load

• A programmable interrupt register

• A watchdog timer with time-out periods of

1.25 or 82 seconds, depending on the programming.

The microcontroller can address the PCD5041 as any

other RAM memory connected to the microcontroller bus.

By writing the ‘Interface-Mode Register’, the

microcontroller can select the interface mode and its own

clock frequency.

6.6.2 MICROCONTROLLER INTERRUPTS

The function of microcontroller Interrupts is to make

optimal use of the microcontroller’s processing power, and

to achieve optimal cooperation between time-critical tasks

and less time-critical tasks both executed in software.

Three registers are available to handle interrupts. These

are:

• Interrupt Event Register

• Interrupt Enable Register

• Interrupt Reset Register.

These registers are to be regarded together.

Corresponding bits in these registers relate to one and the

same event. Bits in the Interrupt Event Register are set by

the PCC and are to be reset by the external processor by

writing ‘1’s in the corresponding bits in the Interrupt Reset

Register. The mask in the Interrupt Enable Register

enables the interrupt if corresponding events do occur.

6.6.3 WATCHDOG

The PCD5041 is equipped with a watchdog timer, which

generates a reset towards an external device (e.g. a

microcontroller) after time-out. Two (fixed) time-out

periods can be programmed; 1.25 s and 82 s.

The watchdog function can be disabled by using the

EN_WATCHDOG input pin.

6.6.4 POWER-DOWN

The PCC may switch off the 6.912 MHz internal clock, to

enter a power saving mode. All blocks, running on this

clock are then switched off (i.e. RF-interface, cipher block,

speech interface, PCC). This is called the power-down

state, and is only used in the handset mode.

The 13.824 MHz clock is never switched off. The Timing

Control, microcontroller interface, and Bus Controller keep

running, in order to remain synchronous with a base

station, and to keep the wake-up circuitry active. During

power-down the external microcontroller has still access to

the common data area.

6.7 Survey of registers

For a survey of all addresses occupied refer to

Tables 1 and 2. Some of the address locations are used

differently for read and write. The addresses 000 to 7DF

are occupied by RAM memory, while the upper 32 bytes

are assigned to the hardware registers. A part of the RAM

memory is allocated for use by the RF block, cipher block,

and the speech interface.

1996 Oct 31

16

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