PCD5043 Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza

componentes Descripción

Lista de partido

PCD5043

DECT burst mode controller

Philips Electronics 

Philips Semiconductors

DECT burst mode controller

Objective specification

PCD5043

The ‘DPLL_sync’ indication should only be used, when

‘SlotSync’ is active. It indicates that the last 4 bits of the

pre-amble field (the training sequence) are received

correctly, and thus indicates that the DPLL was in lock

(synchronized) in time. If the ‘SlotSync’ is active, and the

‘DPLL_sync’ is not, then a sliding interferer might have

been detected.

If ‘SlotSync’ is not detected, effectively no data is received

in that slot. This implies a ‘fast mute’ because speech data

received in the previous frame is not destroyed.

6.5.9 CIPHERING MACHINE

The description of the cipher machine is subject to

confidentiality. The specification of its algorithms are

delivered by ETSI under the terms of a Non-Disclosure

Agreement.

The cipher machine is under control of the TBC, which is

implemented in the PCC. The cipher machine generates

2 fields of ciphering bits:

• A_cipher (40 bits) for A-field messages (ciphers tail

only)

• B_cipher (320 bits) for speech in B-field.

The transmitted ciphered bits are then:

• A_ciphered: = A XOR A_cipher

• B_ciphered: = B XOR B_cipher.

On reception by the peer end point, deciphering consists

of the same operation thanks to the synchronous

generation of A_cipher and B_cipher.

handbook, halfpage

KEY

64 BITS

KEY

64 BITS

CIPHER

MACHINE

A_cipher

(40 bits)

B_cipher

(320 bits)

MBH714

Fig.10 Cipher machine and its sources.

The cipher machine is time-multiplexed on a slot basis.

Initially, the Initialisation Vector (IV) and the key must be

loaded into the cipher machine. Transfer of the IV and key

from the common data area to the cipher machine is done

automatically by the cipher machine. The contents of the

memory space where IV and key are found, are the

responsibility of the PCC, and the external

microprocessor.

6.6 Microcontroller Interface

6.6.1 FUNCTION OF THE MICROCONTROLLER INTERFACE

The microcontroller Interface will provide the following

services.

• Direct interface to processors which have an

INTEL-8051 compatible interface

• General interface to processors that can handle ‘wait

states’ e.g. 68000-family; in this case glue logic is

required

• Processor clock signal of which the frequency is

programmable in order to adjust instantaneously

processor performance to processor work load

• A programmable interrupt register

• A watchdog timer with time-out periods of

1.25 or 82 seconds, depending on the programming.

The microcontroller can address the PCD5043 as any

other RAM memory connected to the microcontroller bus.

By writing the ‘Interface-Mode Register’, the

microcontroller can select the interface mode and its own

clock frequency.

6.6.2 MICROCONTROLLER INTERRUPTS

The function of microcontroller Interrupts is to make

optimal use of the microcontroller’s processing power, and

to achieve optimal cooperation between time-critical tasks

and less time-critical tasks both executed in software.

Three registers are available to handle interrupts. These

are:

• Interrupt Event Register

• Interrupt Enable Register

• Interrupt Reset Register.

These registers are to be regarded together.

Corresponding bits in these registers relate to one and the

same event. Bits in the Interrupt Event Register are set by

the PCC and are to be reset by the external processor by

writing ‘1’s in the corresponding bits in the Interrupt Reset

Register. The mask in the Interrupt Enable Register

enables the interrupt if corresponding events do occur.

1996 Oct 31

14

Share Link: