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PCD6001

Digital telephone answering machine chip

Philips Electronics 

Philips Semiconductors

Digital telephone answering machine chip

Product specification

PCD6001

SYMBOL

PARAMETER

CONDITIONS MIN. TYP. MAX. UNIT

∆G(D/A)

delta digital-to-analog path gain from notes 1 and 27 −1

0

1

dB

DT1/DT2 to SPKR or LIFOUT

F(D/A)(idle)

digital-to-analog idle channel noise

notes 1 and 28 −

−89

−80

dBmp

S/(N+THD)(D/A)(0) digital-to-analog signal-to-(noise + total notes 1 and 29 −

80

−

dBp

S/(N+THD)(D/A)(−40) harmonic distortion) ratio

notes 1 and 30 −42

50

−

dBp

td(g)(D/A)

digital-to-analog path group delay

−

500

−

µs

Notes

1. For the definition of the amplitude units (dB, dBm, dBm0, dBmp, dBm0p) see Section 13.1. All measurements are

performed with chopping switched on (PMTR2 = 04H) and unless mentioned otherwise, all measurements are

performed in RTC mode = 0 (CKCON.6 = 0) and at nominal supply voltage (VDDA = 2.50 V).

2. Maximum sinewave RMS level applied differentially between pins MICP and MICM. The analog-to-digital path gain

for CODEC2 is set to 7 dB (DTCON.1 = 1, DTCON.2 = 0). For larger input levels the output signal will saturate. For

higher analog-to-digital gain settings (including the microphone preamplifier), the maximum RMS input level will

decrease by the same amount as the gain will increase.

3. All input resistances represent the theoretical minimum which can be guaranteed by design. Note that given input

resistance values can vary depending on several conditions as processing, temperature and input signal shape. For

the measurement, the input signal is a 1 kHz sine wave which is AC coupled with a 1 µF capacitor (see Application

example in Fig. 36). The input resistance will increase when others than the noted gains are selected. For detailed

information on input resistances for all gain settings, refer to the PCD6001 application note which is available.

4. The differential resistance is seen between pins MICP and MICM. The minimum resistance will be seen for an

analog-to-digital path gain of 7 dB and will slightly increase for all other gain settings.

5. The common mode resistance is seen between MICP/MICM and VSSA. MICP and MICM are shorted. It corresponds

to RMICVDD ||RMICVSS (see Fig.36). The minimum resistance will be seen for an analog-to-digital path gain of

23/35 dB and will increase for all other gain settings.

6. Maximum sinewave RMS level applied differentially between pins LIFPIN and LIFMIN1/LIFMIN2. VREF is tuned to

2.0 V and the analog-to-digital path gain for CODEC1 is set to 7 dB (CDVC1.3 = 0, DTCON.5 = 0). For larger input

levels the output signal will saturate. For higher analog-to-digital gain settings, the maximum RMS input level will

decrease by the same amount as the gain will increase.

7. The differential resistance is seen between pins LIFPIN and LIFMIN1. The minimum resistance will be seen for an

analog-to-digital path gain of 23/35 dB and will increase for other gain settings.

8. The common mode resistance is seen between LIFPIN/LIFMIN1 and VSSA. LIFPIN and LIFMIN1 are shorted. It

corresponds to RLIF1VDD || RLIF1VSS (see Fig.36). The minimum resistance will be seen for an analog-to-digital path

gain of 7 dB and will increase for other gain settings.

9. The differential resistance is seen between pins LIFPIN and LIFMIN2. The minimum resistance will be seen for an

analog-to-digital path gain of 23/35 dB and will increase for other gain settings.

10. The common mode resistance is seen between LIFPIN/LIFMIN2 and VSSA. LIFPIN and LIFMIN2 are shorted.

It corresponds to RLIF2VDD || RLIF2VSS (see Fig. 36). The minimum resistance will be seen for an analog-to-digital path

gain of 7 dB and will increase for other gain settings.

11. Absolute typical gain for CODEC1 and CODEC2 for gain step 7dB (CDVC1.3 = 0, DTCON.5 = 0 and DTCON.1 = 1),

measured at the DR1/DR2 bitstream interface as defined in Fig.29 using a 1020 Hz sinewave. VREF is tuned to

2.00 V.

12. Absolute typical gain for CODEC1 and CODEC2 for gain step 23 dB (CDVC1.3 = 1, CDVC2.3 = 0 and DTCON.5 = 0,

DTCON.1 = 0), measured at the DR1/DR2 bitstream interface as defined in Fig.29 using a 1020 Hz sinewave. VREF

is tuned to 2.00 V.

2001 Apr 17

81

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