PCF8584 Ver la hoja de datos (PDF) - Philips Electronics
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PCF8584 Datasheet PDF : 40 Pages
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Philips Semiconductors
I2C-bus controller
Product specification
PCF8584
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
tAVCL
tWLCL
tRHCL
tCLDV
tCLDL
tCHAI
tCHRL
tCHWH
tCHDF
tCHDE
tCHDI
tDVCL
tALIE
tALDV
tALAE
tAHDI
tALDL
tAHDE
tW4
tW5
tCLCL
A0 set-up to CS LOW
R/WR set-up to CS LOW
R/WR set-up to CS LOW
data valid after CS LOW
DTACK LOW after CS LOW
A0 hold from CS HIGH
R/WR hold from CS HIGH
R/WR hold from CS HIGH
data bus float after CS HIGH
DTACK HIGH from CS HIGH
data hold after CS HIGH
data set-up to CS LOW
INT HIGH from IACK LOW
data valid after IACK LOW
IACK pulse width
data hold after IACK HIGH
DTACK LOW from IACK LOW
DTACK HIGH from IACK HIGH
RESET pulse width
STROBE pulse width
CS LOW
see Figs 17 and 18 10
see Fig.17
10
see Fig.18
10
see Fig.18 and note 2 −
see Figs 17 and 18 −
see Fig.18
0
see Fig.18
0
see Fig.17
0
see Fig.18
−
see Figs 17 and 18 −
see Fig.17
0
see Fig.17
0
see Figs 19 and 20 −
see Figs 19 and 20 −
see Fig.20
230
see Fig.20
−
see Fig.20
−
see Fig.20
−
see Fig.21
30tCLK
see Fig.22
see Figs 17 and 18
8tCLK
−
−
−
−
160
2tCLK + 75
−
−
−
−
100
−
−
130
200
−
−
2tCLK + 75
120
−
8tCLK + 90
tCLDL + tCHDE
−
ns
−
ns
−
ns
180
ns
3tCLK + 150 ns
−
ns
−
ns
−
ns
150
ns
120
ns
−
ns
−
ns
180
ns
250
ns
−
ns
30
ns
3tCLK + 150 ns
140
ns
−
ns
−
ns
−
ns
Notes
1. A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses when the I2C-bus controller
operates at 8 or 12 MHz. This may be reduced to 3 clock cycles for lower operating frequencies.
2. Not for S1.
1997 Oct 21
25
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