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PE42421 Ver la hoja de datos (PDF) - Peregrine Semiconductor Corp.

Número de pieza
componentes Descripción
Lista de partido
PE42421
PEREGRINE
Peregrine Semiconductor Corp. PEREGRINE
PE42421 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
PE42421
Product Specification
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine’s PE42421. The
RF common port is connected through a 50
transmission line via the top SMA connector, J1.
RF1 and RF2 are connected through 50
transmission lines via SMA connectors J2 and J3,
respectively. A through 50transmission is
available via SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and εr of 4.4.
J6 and J7 provide a means for controlling DC and
digital inputs to the device. J6-1 is connected to
the device VDD or CTRL input. J7-1 is connected
to the device CTRL input.
Figure 5. Evaluation Board Layouts
Peregrine Specification 101-0162-02
Figure 6. Evaluation Board Schematic
Peregrine Specification 102-0756-01
J4
N/A
1
T-line Description
--
Model = CPWG
H = 28 mils
T = 2.1 mils
W = 47 mils
G = 30 mils
Er = 4.4
J1
RFC
1
C1
0.5pF
SEEASSYNOTE 2
C2
0.5pF
SEEASSYNOTE 2
Document No. 70-0396-03 www.psemi.com
1
J5
N/A
J7
CNTL
R2
1 K Ohm
General Comments
Transmission lines connected to J1, J2, and J3 should have exactly the
same electrical length
The path from J2 to J3 including the distance through the part should
have the same length as J4 and J5 and be in parallel to J4 to J5
U1
PE42421/SC70-6
4
5
6
CTRL RF_2
RFC GND
VDD RF_1
3
2
1
1
J3
RF2
1
J2
RF1
R1
1 K Ohm
J6
CNTLX/VDD
Notes: Add two 0.5 pF caps in series to be shunted on the J1 SMA input
Solder C1 side 1 to the RF trace close to the J1 pin
Solder C1 side 2 to C2 side 1
Solder C2 side 2 to ground
©2010-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 9

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