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PEB20954E

Smart Integrated Digital Echo Canceller

Infineon Technologies 

SIDEC

Smart Integrated Digital Echo Canceller

PEF/PEB 20954 HT

Version 1.1

1.1

Key Features

• 2.048 MHz PCM input and output interfaces with

selectable µ- and A-Law coding according to ITU

G.711

• Rapid convergence of patented algorithm at the

beginning or during a connection even in the presence

of background noise at the near end subscriber

P-TQFP-144-6, -8, -14

• Echo return loss enhancement of > 30 dB (ERLE)

• Detection of double talk for adaptive convergence

control

• Independently controlled voiceband echo cancelling

according to ITU G.165 and G.168 for

– 32 channels with end echo path delay of less than

63.75 ms

– 16 channels with end echo path delay of less than

127.75 ms (usage of two SIDEC in parallel for P-LFBGA-160-2

simultaneous processing of 32 channels is easily

possible)

• Smart Non Linear Processor controlled by echoloss, echo path delay and background

noise

• Various options for comfort noise injection

• Maskable disabling functions

– 2100 Hz tone with phase reversal detection

– 2100 Hz tone without phase reversal detection

– 2010 Hz continuity check (SS7)

– via PCM timeslot 16 Bit a, b, c or d according to ITU G.704

– individual channels maskable via Microprocessor Interface, UCC Interface and

Serial Interface

Type

PEF/PEB 20954 HT

PEF/PEB 20954 E

Data Sheet

Package

P-TQFP-144-8

P-LFBGA-160-2

12

2004-07-28

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