SL74HC595N Ver la hoja de datos (PDF) - System Logic Semiconductor
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SL74HC595N
System Logic Semiconductor
SL74HC595N Datasheet PDF : 10 Pages
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SL74HC595
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Minimum Clock Frequency (50% Duty Cycle)
(Figures 1and 7)
tPLH, tPHL Maximum Propagation Delay, Shift Clock to SQH
(Figures 1and 7)
tPHL Maximum Propagation Delay , Reset to SQH
(Figures 2 and 7)
tPLH, tPHL Maximum Propagation Delay , Latch Clock to QA-
QH (Figures 3 and 7)
tPLZ, tPHZ Maximum Propagation Delay , Output Enable to
QA-QH (Figures 4 and 8)
tPZL, tPZH Maximum Propagation Delay , Output Enable to
QA-QH (Figures 4 and 8)
tTLH, tTHL Maximum Output Transition Time, QA-QH (Figures
3 and 7)
tTLH, tTHL Maximum Output Transition Time, SQH
(Figures 1 and 7)
CIN
Maximum Input Capacitance
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State), QA-QH
VCC
Guaranteed Limit
V 25 °C to ≤85
-55°C
°C
≤125
°C
2.0 6.0
4.8
4.0
4.5 30
24
20
6.0 35
28
24
2.0 140
175
210
4.5 28
35
42
6.0 24
30
36
2.0 145
180
220
4.5 29
36
44
6.0 25
31
38
2.0 140
175
210
4.5 28
35
42
6.0 24
30
36
2.0 150
190
225
4.5 30
38
45
6.0 26
33
38
2.0 135
170
205
4.5 27
34
41
6.0 23
29
35
2.0 60
75
90
4.5 12
15
18
6.0 10
13
15
2.0 75
95
110
4.5 15
19
22
6.0 13
16
19
-
10
10
10
-
15
15
15
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
pF
pF
Power Dissipation Capacitance (Per Package)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
300
pF
SLS
System Logic
Semiconductor
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