PI49FCT20807
1-10 Clock Buffer for
Networking Applications 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Graph 1. Dynamic Current vs. Clock Frequency
160
140
120
100
80
60
40
20
0
0
Load = 15pF & 33 ohms
Load = 0
50
100
150
Clock Frequency [MHz]
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(1)
Description
Test Conditions
Typ.
CIN
Input Capacitance
VIN = 0V
3
COUT
Output Capacitance
VOUT = 0V
Note:
1. This parameter is determined by device characterization but is not production tested.
Switching Characteristics (VDD = 2.5V ± 0.2V, TA = 85°C)
Parameters
Description
Test Conditions(1)
tR/tF
CLKn Rise/Fall Time 0.7V ~ 1.7 V
tPLH
tPHL
Propagation Delay BUF_IN to CLKn
tSK(o)(2)
Skew between two outputs of the same package
(same transition)
tSK(p)(2)
Skew between opposite transitions (tPHL-tPLH)
of the same output
tSK(t)(2) Skew between two outputs of different package (4)
Notes:
1. See test circuit and waveforms.
2. Skew measured at worse cast temperature (max. temp).
CL = 22pF, 100 MHz
CL = 12pF, 150 MHz
CL = 22pF, 100 MHz
CL = 12pF, 150 MHz
CL = 22pF, 100 MHz
CL = 12pF, 150 MHz
CL = 22pF, 100 MHz
CL = 12pF, 150 MHz
CL = 12pF, 150 MHz
Test Circuits for All Outputs
200
Max.
4
6
Units
pF
Min.
–
–
–
–
–
–
–
–
–
Typ. Max. Units
1.0 1.25
1.0 1.2
ns
3.0 3.5
2.4 2.7
100 150
100 150
250 300 ps
250 300
400 600
VDD
VIN
VOUT
Pulse
Generator
D.U.T.
CL
Definitions:
CL = Load capacitance: includes jig and probe capacitance.
3
PS8558B 09/24/04