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PI6C105

Precision Clock Synthesizer for Mobile PCs

Pericom Semiconductor 

PI6C105

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SEL100/66# (pin 14) SS1 Byte3 [6] SS0 Byte3 [5] Down Spread

Description

0

0

0

-0.6% 66.6 MHz, -0.6% down spread

0

0

1

-1.2% 66.6 MHz, -1.2% down spread

0

1

0

-1.8% 66.6 MHz, -1.8% down spread

0

1

1

-2.4% 66.6 MHz, -2.4% down spread

1

0

0

-0.6% 100 MHz, -0.6% down spread

1

0

1

-1.0% 100 MHz, -1.0% down spread

1

1

0

-1.5% 100 MHz, -1.5% down spread

1

1

1

-2.0% 100 MHz, -2.0% down spread

Power Management Timing

Signal

Signal State

Latency

No. of rising edges of free running PCICLK

CPU_STOP#

0 (disabled)

1

1 (enabled)

1

PCI_STOP#

0 (disabled)

1

1 (enabled)

1

PWR_DWN# 1 (normal operation)

3ms

0 (power down)

2 max.

Notes:

1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs

between when the clock disable goes low/high to when the first valid clock comes out of

the device.

2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid

clocks are driven from the device.

253

PS8316 03/15/99

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