HI20203 Ver la hoja de datos (PDF) - Intersil
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HI20203 Datasheet PDF : 10 Pages
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HI20203
Electrical Specifications AVEE = -5.2V, DVEE = -5.2V, AGND = 0V, DGND = 0V, RL = ∞, VOUT = -1V, TA = 25oC (Continued)
HI20203JCB/JCP
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Input Logic Current, IIL, IIH
(For D9 thru D6, COMPL)
VIH = -0.89V, VIL = -1.75V
(Note 2)
0.1
1.5
6.0
µA
Input Logic Current, IIL, IIH
(For D5 thru D0)
VIH = -0.89V, VIL = -1.75V
(Note 2)
0.1
0.75
3.0
µA
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 11
Data Hold Time, tHLD
See Figure 11
Propagation Delay Time, tPD
Settling Time, tSET (to 1/2 LSB)
See Figure 11
See Figure 11
POWER SUPPLY CHARACTERISITICS
5
-
-
ns
1
-
-
ns
-
3.8
-
ns
-
4.3
-
ns
IEE
Power Dissipation
75Ω load
-60
-75
-90
mA
-
420
470
mW
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. Excludes error due to reference drift.
4. Electrical specifications guaranteed only under the stated operating conditions.
Timing Diagram
CLK
CLK
DATA
tSU
N
0V
D/A OUT
-1V
tHD
tD
N+1
90%
N
50%
10%
tr
tD
N+1
tf
FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS)
10-4
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