AD9283
AIN
ENCODE
D7–D0
33.3k⍀
AIN
14.3k⍀
SAMPLE N
SAMPLE N+1
SAMPLE N+4
SAMPLE N+5
tA
tEH
tEL
SAMPLE N+2 SAMPLE N+3
1/fS
DATA N–4
DATA N–3
DATA N–2
tPD
DATA N–1
DATA N
Figure 1. Timing Diagram
VDD
33.3k⍀
AIN
14.3k⍀
tV
DATA N+1
VDD
OUT
Figure 2. Equivalent Analog Input Circuit
VD
VBIAS
REF IN
Figure 5. Equivalent Digital Output Circuit
VD
OUT
Figure 3. Equivalent Reference Input Circuit
VD
ENCODE
Figure 4. Equivalent Encode Input Circuit
Figure 6. Equivalent Reference Output Circuit
REV. C
–5–