PLL102-108
Programmable DDR Zero Delay Clock Driver
7. Byte 6: Buffer Drive Strength Control Register
Bit
Name
Default
Description
Bit 7
-
1
Reserved.
Bit 6
-
1
Reserved.
Bit 5
-
1
Reserved.
Bit 4
-
1
Reserved.
Bit 3
-
1
Reserved.
Bit 2
Bit <2>
Bit 1
FBOUT
Strength
Bit <1>
Bit 0
Bit <0>
0
1
These three bits will program drive strength for FBOUTT output
clock (see Table 3).
1
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Rev 03/29/02 Page 7