PSB2168 Ver la hoja de datos (PDF) - Siemens AG

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PSB2168

General-Purpose Power Controller

Siemens AG 

PSB 2168

List of Figures

Page

Figure 35: SSDI Interface - Active Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 36: SSDI Interface - Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 37: Status Register Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 38: Data Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 39: Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 40: Configuration Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 41: Configuration Register Write Access or Register Read Command . . . . . 74

Figure 42: ARAM/DRAM Interface - Connection Diagram. . . . . . . . . . . . . . . . . . . . . 77

Figure 43: ARAM/DRAM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . 78

Figure 44: ARAM/DRAM Interface - Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . 79

Figure 45: ARAM/DRAM Interface - Refresh Cycle Timing . . . . . . . . . . . . . . . . . . . . 79

Figure 46: EPROM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 47: EPROM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 48: Flash Memory Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . 81

Figure 49: Flash Memory Interface - Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 50: Flash Memory Interface - Command Write. . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 51: Flash Memory Interface - Address Write . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 52: Flash Memory Interface - Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 53: Flash Memory Interface - Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 54: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Electrical Characteristics

Figure 55: Input/Output Waveforms for AC-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Timing Diagrams

Figure 56: Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 57: SSDI/IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . 167

Figure 58: SSDI/IOM®-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . 167

Figure 59: SSDI Interface - Strobe Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 60: Serial Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 61: Clock Master Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 62: Memory Interface - DRAM Read Access . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 63: Memory Interface - DRAM Write Access . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 64: Memory Interface - DRAM Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 65: Memory Interface - EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 66: Memory Interface - Samsung Command Write . . . . . . . . . . . . . . . . . . . 176

Figure 67: Memory Interface - Samsung Address Write . . . . . . . . . . . . . . . . . . . . . 177

Figure 68: Memory Interface - Samsung Data Write . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 69: Memory Interface - Samsung Data Read . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 70: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 71: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Semiconductor Group

6

11.97

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