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H8S/2189R

16-Bit Single-Chip Microcomputer

Renesas Electronics 

Preface

This H8S/2189R Group is a series of microcomputers (MCUs) made up of the H8S/2000 CPU

with Renesas Technology’s original architecture as its core, and the peripheral functions required

to configure a system.

The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a

simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a

16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward

compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the transition

from the H8/300, H8/300L, or H8/300H to the H8S/2000 CPU.

Target Users: This manual was written for users who use the H8S/2189R in the design of

application systems. Target users are expected to understand the fundamentals of

electrical circuits, logic circuits, and microcomputers.

Objective:

This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2189R Group to the target users.

Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a

detailed description of the instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read this manual in the order of the table of contents. This manual can be roughly categorized

into the descriptions on the CPU, system control functions, peripheral functions and electrical

characteristics.

• In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

• In order to understand the detailed function of a register whose name is known

Read the index that is the final part of the manual to find the page number of the entry on the

register. The addresses, bits, and initial values of the registers are summarized in section 24,

List of Registers.

Rules:

Register name: The following notation is used for cases when the same or a

similar function, e.g., serial communication interface, is

implemented on more than one channel:

XXX_N (XXX is the register name and N is the channel

number)

Rev. 2.00 Aug. 03, 2005 Page vi of xlii

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