GS88218B-66 Ver la hoja de datos (PDF) - Giga Semiconductor
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GS88218B-66 Datasheet PDF : 39 Pages
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Preliminary
GS88218/36B-11/11.5/100/80/66
ByteSafe™ Parity Functions
In x32/x16 mode this RAM features a parity encoding and checking function. It is assumed that the RAM is being used in x32/x16
mode because there is no source for parity bits from the system. So, in x32/x16 mode, the device generates parity and stores it
along with written data. It is also assumed that there is no facility for parity checking, so the RAM checks read parity and reports an
error in the cycle following parity check.
In x32/x16 mode the device does not drive the 9th data output, even though the internal ByteSafe parity encoding has been
activated. A ByteSafe SRAM, used in x32/x16 mode, allows parity protection of data in applications where parity encoding or
checking are not otherwise available. As in any system that checks read parity, reads of un-written memory locations may well
produce parity errors. Initialization of the memory should be implemented to avoid this issue.
In x18/x36 mode this SRAM includes a write data parity check that checks the validity of data coming into the RAM on write
cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write
data errors are reported one clock cycle later. (See timing diagram below.) The Data Parity Mode (DP) pin must be tied high to set
the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data validity is
best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a parity error.
Multiple Parity Error Output pins may share a common pull-up resistor.
x32 Mode (PE = 1) Read Parity Error Output Timing Diagram
CK
Address A Address B Address C Address D Address E Address F
DQ
D Out A
D Out B
D Out C
D Out D
D Out E
tKQ
tHZ
tLZ
tKQX
QE
Err A
Err C
DQ
D Out A
D Out B
D Out C
D Out D
tKQ
tHZ
tLZ
tKQX
QE
Err A
Err C
Rev: 1.15 5/2001
8/39
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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