CY7C025AV-20AI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C025AV-20AI Datasheet PDF : 18 Pages
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PRELIMINARY
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Characteristics Over the Operating Range[14] (continued)
Parameter
BUSY TIMING[20]
Description
tBLA
BUSY LOW from Address Match
tBHA
BUSY HIGH from Address Mismatch
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port Set-Up for Priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[21]
BUSY HIGH to Data Valid
INTERRUPT TIMING[20]
tINS
INT Set Time
tINR
INT Reset Time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
tSAA
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
-15[1]
-20
-25
Min. Max. Min. Max. Min. Max.
Unit
15
20
20
ns
15
20
20
ns
15
20
20
ns
15
17
17
ns
5
5
5
ns
0
0
0
ns
13
15
17
ns
15
20
25
ns
15
20
20
ns
15
20
20
ns
10
10
12
ns
5
5
5
ns
5
5
5
ns
15
20
25
ns
Data Retention Mode
The CY7C024AV/025AV/026AV and CY7C0241AV/0251AV/
036AV are designed with battery backup in mind. Data reten-
tion voltage and supply current are guaranteed over tempera-
ture. The following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 volts).
Timing
VCC
CE
Data Retention Mode
3.0V
VCC > 2.0V
3.0V
VCC to VCC – 0.2V
tRC
VIH
Parameter
Test Conditions[22] Max. Unit
ICCDR1
@ VCCDR = 2V
50
µA
Notes:
20. Test conditions used are Load 2.
21. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
22. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
8
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