CY7C4241-10JI Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

fabricante

CY7C4241-10JI

64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421/4201/4211/4221

CY7C4231/4241/4251

RS

REN1,

REN2

WEN1

WEN2/LD[17]

EF,PAE

FF,PAF,

Q0 - Q8

Figure 7. Reset Timing[16]

tRS

tRSS

tRSR

tRSS

tRSR

tRSS

tRSR

tRSF

tRSF

tRSF

OE = 1[18]

OE = 0

Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write

WCLK

tDS

D0–D8

D0 (FIRSTVALID Write)

D1

tENS

WEN1

WEN2

(if applicable)

[19]

tFRL

RCLK

tSKEW1

tREF

EF

REN1,

REN2

Q0 –Q8

OE

tOLZ

tOE

D2

tA []

D3

tA

D0

D4

D1

Notes

16. The clocks (RCLK, WCLK) can be free-running during reset.

17. Holding WEN2/LD HIGH during reset makes the pin act as a second enable pin. Holding WEN2/LD LOW during reset makes the pin act as a load enable for the

programmable flag offset registers.

18. After reset, the outputs are LOW if OE = 0 and three-state if OE = 1.

19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK +

tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).

20. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06016 Rev. *D

Page 12 of 20

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