RT8055BQWG Ver la hoja de datos (PDF) - Richtek Technology
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RT8055BQWG Datasheet PDF : 13 Pages
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Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, VDD. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8055B, the maximum junction temperature is 125°C
and TA is the maximum ambient temperature. The junction
to ambient thermal resistance θJA is layout dependent.
For WDFN-10L 3x3 packages, the thermal resistance θJA
is 60°C/W on the standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by following formula :
PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for
WDFN-10L 3x3 package
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. For RT8055B package, the Figure 3 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation allowed.
RT8055B
2.00
Four Layers PCB
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curves for RT8055B Package
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8055B.
` A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
` Connect the terminal of the input capacitor(s), CIN, as
close as possible to the PVDD pin. This capacitor
provides the AC current into the internal power
MOSFETs.
` LX node is with high frequency voltage swing and should
be kept within small area. Keep all sensitive small-signal
nodes away from the LX node to prevent stray capacitive
noise pick-up.
` Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of powercomponents.
You can connect the copper areas to any DC net (PVDD,
VDD, VOUT, PGND, GND, or any other DC rail in your
system).
` Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and GND.
DS8055B-03 April 2011
www.richtek.com
11
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