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HM62G36256

8M Synchronous Fast Static RAM (256k-word × 36-bit)

Hitachi -> Renesas Electronics 

HM62G36256 Series

Single Differential Clock Register-Register Mode (M1 = VSS, M2 = VDD)

HM62G36256

-4

-5

Parameter

Symbol Min Max Min Max Unit Notes

CK clock cycle time

CK clock high width

CK clock low width

Address setup time

Data setup time

Address hold time

Data hold time

Clock high to output valid

Clock high to output hold

Clock high to output valid

(SS control)

t KHKH

t KHKL

t KLKH

t AVKH

t DVKH

t KHAX

t KHDX

t KHQV

t KHQX

t KHQX2

4.0 — 5.0 — ns

1.5 — 1.5 — ns

1.5 — 1.5 — ns

0.5 — 0.5 — ns

0.5 — 0.5 — ns

0.75 — 1.0 — ns 1

0.75 — 1.0 — ns 1

— 2.1 — 2.5 ns 2

0.5 — 0.5 — ns 2

— 2.1 — 2.5 ns 2, 5

Clock high to output High-Z

t KHQZ

— 2.5 — 3.0 ns 2, 3

Output enable low to output Low-Z tGLQX

0.5 — 0.5 — ns 2, 5

Output enable low to output valid tGLQV

— 2.5 — 2.5 ns 2, 3

Output enable low to output High-Z tGHQZ

— 2.5 — 2.5 ns 2, 3

Sleep mode recovery time

t ZZR

10.0 — 10.0 — ns 6

Sleep mode enable time

t ZZE

— 10.0 — 10.0 ns 2, 3, 6

Notes: 1. Guaranteed by design.

2. Refer to the Test Conditions.

3. Transitions are measured at start point of output high impedance from output low impedance.

4. Output driver impedance updates during High-Z.

5. Transitions are measured ±50 mV from steady state voltage.

6. When ZZ is switching, clock input K must be at same logic levels for reliable operation.

10

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