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RT9210GC

Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination

Richtek Technology 

RT9210

Preliminary

NC (Pin 10 , 16 , 18)

No internal connection.

SENSE2 (Pin 17)

This pin is connected directly to the regulated output of

VTT supply. This pin is also used as the feedback pin of

the VTT regulator and as the regulation point for the window

regulator that is enable in V2_SD mode.

PGOOD (Pin 19)

PGOOD is an open-drain output used to indicate that both

the VDDQ and VTT regulators are within normal operating

voltage ranges.

V2_SD (Pin 20)

A TTL compatible high level at this pin puts the VTT

controller into“sleep”mode. In sleep mode, both UGATE2

and LGATE2 are driven low, effectively floating the VTT

supply. While the VTT supply “floats”, it is held to about

50% of VDDQ via a low current window regulator which

drivers VTT via the SENSE2 pin. The window regulator

can overcome up to at least ±10mA of leakage on VTT.

While V2_SD is high, PGOOD is low.

OCSET/SD (Pin 21)

Connect a resistor (ROCSET) from this pin to the drain of

the upper MOSFET of the VDDQ regulator sets the over-

current trip point. ROCSET, an internal 40μA current source

, and the upper MOSFET on-resistance, RDS(ON), set the

VDDQ converter over-current trip point (IOCSET) according

to the following equation:

40uA × ROCSET

IOCSET =

R DS(ON) of the upper MOSFET

An over-current trip cycles the soft-start function. Pulling

the pin to ground resets the device and all external

MOSFETs are turned off allowing the two output voltage

power rails to float.

PVCC1 (Pin 22)

Connect this pin to a well-decoupled 5V supply. It is also

the positive supply for the lower gate driver, LGATE1.

LGATE1 (Pin 23)

VDDQ lower gate drive output. Connect to gate of the low-

side power N-MOSFET. This pin is monitored by the

adaptive shoot-through protection circuitry to determine

when the lower MOSFET has turned off.

PGND1 (Pin 24)

Return pin for high currents flowing in low-side power

N-MOSFET. Ties the pin directly to the low-side MOSFET

source and ground plane with the lowest impedance.

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DS9210-05 March 2007

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