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RT9232

Programmable Frequency Synchronous Buck PWM Controller

Richtek Technology 

RT9232

ΔIL = (VIN − VOUT) x

V OUT

(5)

VIN x fOSC x L

Generally, an inductor that limits the ripple current between

20% and 50% of output current is appropriate. Make sure

that the output inductor could handle the maximum output

current and would not saturate over the operation

temperature range.

Output Capacitor Selection

The output capacitors determine the output ripple voltage

(ΔVOUT) and the initial voltage drop after a high slew-rate

load transient. The selection of output capacitor depends

on the output ripple requirement. The output ripple voltage

is described as Equation (6).

ΔVOUT

=

ΔIL

x

ESR +

1

8

x

fO2SC

VOUT

x L x COUT

(1− D)

(6)

For electrolytic capacitor application, typically 90~95%

of the output voltage ripple is contributed by the ESR of

output capacitors. Paralleling lower ESR ceramic capacitor

with the bulk capacitors could dramatically reduce the

equivalent ESR and consequently the ripple voltage.

Input Capacitor Selection

Use mixed types of input bypass capacitors to control

the input voltage ripple and switching voltage spike across

the MOSFETs. The buck converter draws pulsewise

current from the input capacitor during the on time of upper

MOSFET. The RMS value of ripple current flowing through

the input capacitor is described as:

IIN(RMS) = IOUT x D x (1− D)

(7)

The input bulk capacitor must be cable of handling this

ripple current. Sometime, for higher efficiency the low ESR

capacitor is necessarily. Appropriate high frequency

ceramic capacitors physically near the MOSFETs

effectively reduce the switching voltage spikes.

MOSFET Selection

The selection of MOSFETs is based upon the

considerations of RDS(ON), gate driving requirements, and

thermal management requirements. The power loss of

upper MOSFET consists of conduction loss and switching

loss and is expressed as:

PUPPER = PCOND _UPPER + PSW_UPPER

(8)

= IOUT

x RDS(ON)

xD+

1

2

IOUT

x

VIN

x (TRISE

+ TFALL ) x

f OSC

where TRISE and TFALL are rising and falling time of VDS of

upper MOSFET respectively. RDS(ON) and QG should be

simultaneously considered to minimize power loss of upper

MOSFET.

The power loss of lower MOSFET consists of conduction

loss, reverse recovery loss of body diode, and conduction

loss of body diode and is express as:

PLOWER = PCOND _LOWER + PRR + PDIODE

(9)

= IOUT x RDS(ON) x (1− D) + QRR x VIN x fOSC

+

1

2

x IOUT

x

VF

x

TDIODE

x

f OSC

where TDIODE is the conducting time of lower body diode.

Special control scheme is adopted to minimize body diode

conducting time. As a result, the RDS(ON) loss dominates

the power loss of lower MOSFET. Use MOSFET with

adequate RDS(ON) to minimize power loss and satisfy

thermal requirements.

Feedback Compensation

Figure 4 highlights the voltage-mode control loop for a

synchronous buck converter. Figure 5 shows the

corresponding Bode plot. The output voltage (VOUT) is

regulated to the reference voltage. The error amplifier EA

output (COMP) is compared with the oscillator (OSC)

sawtooth wave to provide a pulse-width modulated (PWM)

wave with an amplitude of VIN at the PHASE node. The

PWM wave is smoothed by the output filter (L and COUT).

The modulator transfer function is the small-signal transfer

function of VOUT/COMP. This function is dominated by a

DC gain and the output filter (L and COUT), with a double

pole break frequency at FP_LC and a zero at FZ_ESR. The

DC gain of the modulator is simply the input voltage (VIN)

divided by the peak-to-peak oscillator voltage ΔVOSC.

The break frequency FLC and FESR are expressed as

Equation (10) and (11) respectively.

FP_LC = 2π

1

LCOUT

(10)

FZ_ESR

=

2π

1

x ESR

x COUT

(11)

DS9232-06 March 2007

www.richtek.com

11

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