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RTL8100C

SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

RTL8100C & RTL8100CL

Datasheet

5.2. PCI Interface

Symbol

AD31-0

C/BE3-0

CLK

DEVSELB

FRAMEB

GNTB

REQB

IDSEL

INTAB

Type

T/S

T/S

I

S/T/S

S/T/S

I

T/S

I

O/D

Table 2. PCI Interface

Pin No

Description

33, 34, 36, 37, 39, 40, PCI Address and Data Multiplexed Pins.

42, 43, 47, 49, 50, 53,

55, 57, 58, 59, 79, 82,

83, 85, 86, 87, 89, 90,

93, 95, 96, 97, 98, 103,

104

44, 60, 77, 92

PCI Bus Command and Byte Enables Multiplexed Pins.

28

Clock.

This PCI Bus clock provides timing for all transactions and bus

phases, and is input to PCI devices. The rising edge defines the start

of each phase. The clock frequency ranges from 0 to 40MHz. For

normal network operation, the RTL8100C(L) requires a minimum

PCI clock frequency of 16.75MHz.

68

Device Select.

As a bus master, the RTL8100C (L) samples this signal to ensure that

a PCI target recognizes the destination address for the data transfer.

As a target, the RTL8100C(L) asserts this signal low when it

recognizes its target address after FRAMEB is asserted.

61

Cycle Frame.

As a bus master, this pin indicates the beginning and duration of an

access. FRAMEB is asserted low to indicate the start of a bus

transaction. While FRAMEB is asserted, data transfer continues.

When FRAMEB is deasserted, the transaction is in the final data

phase.

As a target, the device monitors this signal before decoding the

address to check if the current transaction is addressed to it.

29

Grant.

This signal is asserted low to indicate to the RTL8100C(L) that the

central arbiter has granted ownership of the bus to the RTL8100C(L).

This input is used when the RTL8100C(L) is acting as a bus master.

30

Request.

The RTL8100C(L) will assert this signal low to request the

ownership of the bus from the central arbiter.

46

Initialization Device Select.

This pin allows the RTL8100C(L) to identify when configuration

read/write transactions are intended for it.

25

INTAB.

Used to request an interrupt. It is asserted low when an interrupt

condition occurs, as defined by the Interrupt Status, Interrupt Mask

and Interrupt Enable registers.

Single-Chip Fast Ethernet Controller

6

Track ID: JATR-1076-21 Rev. 1.06

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