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RTL8029AS

Realtek PCI Full-Duplex Ethernet Controller with built-in SRAM

Unspecified 

RTL8029AS Preliminary

Command: Command Register (05-04H; Type=R except Bit1, 0=R/W)

The Command register is a 16-bit register used to provide coarse control over a device's ability to

generate and respond to PCI cycles.

Bit

15-10

9

8

7

6

5

4

3

2

1

0

Symbol

-

FBTBEN

SERREN

ADSTEP

PERREN

VGASNOOP

MWIEN

SCYCEN

BMEN

MEMEN

IOEN

Description

Reserved area. Read as 0, write operation has no effect.

Fast Back-To-Back ENable. Read as 0, write operation has no effect. The

RTL8029AS will not generate Fast Back-to-Back cycles.

SERR ENable. Read as 0, write operation has no effect.

Address/Data STEPping. Read as 0, write operation has no effect. The

RTL8029AS never do address/data stepping.

This bit controls the device's response to parity errors. When the value of this bit

is 0, the device must ignore any parity errors that it detects and continues normal

operation. Read as 0, write operation has no effect.

VGA palette SNOOP. Read as 0, write operation has no effect.

Memory Write and Invalidate cycle ENable. Read as 0, write operation has no

effect.

Special CYCle ENable. Read as 0, write operation has no effect. The

RTL8029AS ignores all special cycle operation.

Bus Master ENable. Read as 0, write operation has no effect.

Controls a device's response to memory space accesses.

0 : Disable the device response

1 : Enable the device response

Controls a device's response to I/O space accesses.

0 : Disable the device response

1 : Enable the device response

Status: Status Register (07-06H; Type=R)

The Status register is a 16-bit register used to record status information for PCI bus related events.

Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not

set.

Bit

Symbol

Description

15

DPE

Detected Parity Error. Read as 0, write operation has no effect.

14

SSE

Signaled System Error. Read as 0, write operation has no effect.

13

RMA

Received Master Abort. Read as 0, write operation has no effect.

12

RTA

Received Target Abort. Read as 0, write operation has no effect.

11

STA

Signaled Target Abort. Read as 0, write operation has no effect.

10-9

DST1-0 These bits encode the timing of DEVSELB. They are set to 01b (medium),

indicating the RTL8029AS controller will assert DEVSELB two clocks after

FRAMEB is asserted.

8

DPD

Data Parity Detected. Read as 0, write operation has no effect.

7

FBBC

Fast Back-to-Back Capable. Read as 0, write operation has no effect.

6-0

-

Reserved area. Read as 0, write operation has no effect.

RID: Revision ID Register (08H; Type=R)

The Revision ID register is an 8-bit register that specifies the RTL8029AS controller revision

number. Revision ID = 00H

LS009.0

22

1997.01.16

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