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RTL8181

Wireless LAN Access Point/Gateway Controller

Realtek Semiconductor 

RTL8181

There are two registers for the interrupt control. The GIMR register can enable/disable the interrupt source. The GISR shows

the pending interrupt status.

Interrupt Control Register Set

Virtual address Size (byte) Name

0xBD01_0000 2

GIMR

0xBD01_0004 2

GISR

Description

Global interrupt mask register

Global interrupt status register

Global Interrupt Mask Register (GIMR)

Bit Bit Name Description

0

TCIE

Timers/Counters interrupt enable.

0: Disable, 1: Enable

1

GPIOIE

GPIO interrupt enable.

0: Disable, 1: Enable

2

WLAIE

WLAN controller interrupt enable.

0: Disable, 1: Enable

3

UARTIE UART interrupt enable.

0: Disable 1: Enable

4

ETH0IE

Ethernet0 interrupt enable.

0: Disable, 1: Enable

5

ETH1IE

Ethernet1 interrupt enable.

0: Disable, 1: Enable

6

PCIIE

PCI interrupt enable.

0: Disable, 1: Enable

7

Reserved

8

LBC1E

LBC time-out interrupt enable.

0: Disable, 1: Enable

R/W

InitVal

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Global Interrupt Status Register (GISR)

Bit Bit Name Description

0

TCIP

Timers/Counters interrupt pending flag.

0: no pending, 1: pending

1

GPIOIP

GPIO interrupt pending flag.

0: no pending, 1: pending

2

WLAIP

WLAN controller interrupt pending flag.

0: no pending, 1: pending

3

UARTIP

UARTI interrupt pending flag.

0: no pending, 1: pending

4

ETH0IP

Ethernet0 interrupt pending flag.

0: no pending, 1: pending

5

ETH1IP

Ethernet1 interrupt pending flag.

0: no pending, 1: pending

6

PCIIP

PCI interrupt pending flag.

0: no pending, 1: pending

7

Reserved

8

LBCIP

LBC time-out interrupt pending flag.

0: no pending, 1: pending

R/W

R

R

R

R

R

R

R

InitVal

0

0

0

0

0

0

0

R

0

7. Memory Controller

RTL8181 provides a memory control module that could access external asynchronous SDRAM and flash memory.

RTL8181 could interface to PC100 or PC133-compliant SDRAM, and supports with auto-refresh mode, which requires

4096-cycle refresh in 64 ms. The SDRAM could be accessed in two banks (CS0#, and CS1#), and its size and timing are

configurable in register. The data width of SDRAM could be chosen as 16-bit or 32-bit in register as well. If 32-bit is

configured, 2 banks of 16-bit SDRAM may be used to expand its data width to 32 bits or use one bank of 32-bit SDRAM is

allowable.

CONFIDENTIAL

18

v1.0

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