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S3C24A0A

32-BIT RISC MICROPROCESSOR

Samsung 

Table of Contents (Continued)

Chapter 31 Secure Digital Interface

Overview........................................................................................................................................................31-1

Feature .................................................................................................................................................31-1

Block Diagram ......................................................................................................................................31-2

SDI Operation................................................................................................................................................31-3

SDIO Operation.............................................................................................................................................31-4

SDI Special Registers ...................................................................................................................................31-5

SDI Control Register (SDICON) ...........................................................................................................31-5

SDI Baud Rate Prescaler Register (SDIPRE) ......................................................................................31-6

SDI Command Argument Register (SDICARG) ...................................................................................31-6

SDI Command Control Register (SDICCON).......................................................................................31-6

SDI Command Status Register (SDICSTA) .........................................................................................31-7

SDI Response Register0 (SDIRSP0) ...................................................................................................31-7

SDI Response Register1 (SDIRSP1) ...................................................................................................31-7

SDI Response Register2 (SDIRSP2) ...................................................................................................31-8

SDI Response Register3 (SDIRSP3) ...................................................................................................31-8

SDI Data / Busy Timer Register (SDIDTIMER) ....................................................................................31-8

SDI Block Size Register (SDIBSIZE)....................................................................................................31-8

SDI Data Control Register (SDIDCON)................................................................................................31-9

SDI Data Remain Counter Register (SDIDCNT)..................................................................................31-10

SDI Data Status Register (SDIDSTA) ..................................................................................................31-11

SDI FIFO Status Register (SDIFSTA) ..................................................................................................31-12

SDI Interrupt Mask Register (SDIIMSK)...............................................................................................31-13

SDI Data Register (SDIDATn) ..............................................................................................................31-14

Chapter 32 Memory Stick

Overview........................................................................................................................................................32-1

Features................................................................................................................................................32-1

Memory Stick Protocol..........................................................................................................................32-2

Mandatory Hardware Configuration .....................................................................................................32-2

Host Block Pin Description ...................................................................................................................32-3

Memory Stick Special Registers ...................................................................................................................32-4

Prescaler Control (MSPRE) Register ...................................................................................................32-4

FIFO Interrupt Control (MSFINTCON) Register ...................................................................................32-4

Transfer Protocol Command (TP_CMD) Register ...............................................................................32-5

Control and Status (CTRLSTA) Register .............................................................................................32-6

Data FIFO (DAT_FIFO) Register..........................................................................................................32-7

Interrupt Control and Status (INTCTRLSTA) Register .........................................................................32-7

INS Port Control (INSCON) Register ...................................................................................................32-8

Auto Command/POL Control (ACMD_CON) Register .........................................................................32-8

Auto Transfer Protocol Command (ATP_CMD) Register.....................................................................32-8

S3C24A0A MICROPROCESSOR

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